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Journals Heading link

  1. Remya Ramachandran, Wei Li, Shwetha Khande, Ahish Shylendra, Amit Ranjan Trivedi, Qian Xie, Christine Wu, and Mathew Thoppil Mathew. “Advanced Electrochemical Reamer (EC-Reamer) for Root Canal Treatment.” European Endodontic Journal 8, no. 1 (2023): 79-89.
  2. Nasrin, Shamma, Ahish Shylendra, Nastaran Darabi, Theja Tulabandhula, Wilfred Gomes, Ankush Chakrabarty, and Amit Ranjan Trivedi. “ENOS: Energy-Aware Network Operator Search in Deep Neural Networks.” IEEE Access, 2022.
  3. Leila Rahimifard, Ahish Shylendra, Shamma Nasrin, Stephanie E. Liu, Vinod K. Sangwan, Mark C. Hersam, and Amit Ranjan Trivedi. “Higher order neural processing with input-adaptive dynamic weights on MoS2 memtransistor crossbars.” Frontiers in Electronic Materials, 2022.
  4. Shubhra Deb Paul, Fengchao Zhang, Patanjali SLPSK, Amit Ranjan Trivedi, and Swarup Bhunia, “RIHANN: Remote IoT Hardware Authentication with Intrinsic Identifiers.” IEEE Internet of Things Journal, 2022.
  5. Priyesh Shukla, Ankith Muralidhar, Nick Iliev, Theja Tulabandhula, Sawyer Fuller, and Amit Ranjan Trivedi, “Ultra-low-Power Localization of Insect-Scale Drones: Interplay of Probabilistic Filtering and Compute-in-Memory.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021.
  6. Dinesh Rajasekharan, Amol Gaidhane, Amit Ranjan Trivedi, and Yogesh Singh Chauhan, “Ferroelectric FET-based Implementation of FitzHugh-Nagumo Neuron Model.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021.
  7. Jiangtan Yuan, Stephanie Liu, Ahish Shylendra, William Gaviria Rojas, Silu Guo, Hadallia Bergeron, Shaowei Li, Hong-Sub Lee, Shamma Nasrin, Vinod Sangwan, Amit Ranjan Trivedi, Mark Hersam, “Reconfigurable MoS2 Memtransistors for Continuous Learning in Spiking Neural Networks,” ACS Nano Letters, 2021.
  8. Shamma Nasrin, Diaa Badawi, Ahmet Enis Cetin, Wilfred Gomes, and Amit Ranjan Trivedi. “MF-Net: Compute-In-Memory SRAM for Multibit Precision Inference Using Memory-Immersed Data Conversion and Multiplication-Free Operators.” IEEE Transactions on Circuits and Systems I: Regular Papers 68, no. 5 (2021): 1966-1978.
  9. Fengchao Zhang, Shubhra Deb Paul, Patanjali Slpsk, Amit Ranjan Trivedi, and Swarup Bhunia. “On Database-Free Authentication of Microelectronic Components.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020.
  10. Bogil Kim, Sungjae Lee, Amit Ranjan Trivedi, and William J. Song. “Energy-Efficient Acceleration of Deep Neural Networks on Realtime-Constrained Embedded Edge Devices.” IEEE Access, 2020.
  11. Shamma Nasrin Justine Drobitch, Priyesh Shukla, Theja Tulabandhula, Supriyo Bandyopadhyay, and Amit Ranjan Trivedi, “Bayesian reasoning machine on a magneto-tunneling junction network,” Nanotechnology, 2020.
  12. Madhu Padmanabha Sumangala, Ahish Shylendra, David J. Frank, Takashi Ando, and Amit Ranjan Trivedi. “A Simulation Study on Minimizing Threshold Voltage Variability by Optimizing Oxygen Vacancy Concentration Under Metal Gate Granularity.” IEEE Electron Device Letters, 2020.
  13. Ahish Shylendra, Priyesh Shukla, Saibal Mukhopadhyay, Swarup Bhunia, and Amit Ranjan Trivedi. “Low Power Unsupervised Anomaly Detection by Nonparametric Modeling of Sensor Statistics.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020.
  14. Megan E. Beck, Ahish Shylendra, Vinod K. Sangwan, Silu Guo, William A. Gaviria Rojas, Hocheon Yoo, Hadallia Bergeron, Katherine Su, Amit R. Trivedi, and Mark C. Hersam. “Spiking neurons from tunable Gaussian heterojunction transistors.” Nature communications, 2020.
  15. Nick Iliev and Amit Ranjan Trivedi. “Low-Power Sensor Localization in Three-Dimensional Using a Recurrent Neural Network.” IEEE Sensors Letters, 2019.
  16. Nick Iliev, Alberto Gianelli, and Amit Ranjan Trivedi. “Low Power Speaker Identification by Integrated Clustering and Gaussian Mixture Model Scoring.” IEEE Embedded Systems Letters, 2019.
  17. Ahish Shylendra, Swarup Bhunia, and Amit Ranjan Trivedi. “An Intrinsic and Database-Free Authentication by Exploiting Process Variation in Back-End Capacitors.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019.
  18. Shamma Nasrin, Justine L. Drobitch, Supriyo Bandyopadhyay, and Amit Ranjan Trivedi. “Low power restricted Boltzmann machine using mixed-mode magneto-tunneling junctions.” IEEE Electron Device Letters, 2019.
  19. Tapas Dutta, Girish Pahwa, Amit Ranjan Trivedi, Saurabh Sinha, Amit Agarwal, and Yogesh Singh Chauhan. “Performance evaluation of 7-nm node negative capacitance FinFET-based SRAM.” IEEE Electron Device Letters, 2017.
  20. Susmita Dey Manasi, Md Mamun Al-Rashid, Jayasimha Atulasimha, Supriyo Bandyopadhyay, and Amit Ranjan Trivedi, “Skewed Straintronic Magnetotunneling-Junction-Based Ternary Content-Addressable Memory-Part II,” IEEE Transactions on Electron Devices, 2017.
  21. Susmita Dey Manasi, Md Mamun Al-Rashid, Jayasimha Atulasimha, Supriyo Bandyopadhyay, and Amit Ranjan Trivedi, “Skewed Straintronic Magnetotunneling-Junction-Based Ternary Content-Addressable Memory-Part I,” IEEE Transactions on Electron Devices, 2017.
  22. Tapas Dutta, Girish Pahwa, Amit Ranjan Trivedi, Saurabh Sinha, Amit Agarwal, and Yogesh Singh Chauhan, “Performance Evaluation of 7 nm Node Negative Capacitance FinFET based SRAM,” IEEE Electron Device Letters, 2017.
  23. Tonmoy Dhar and Amit Ranjan Trivedi, “Area and energy-efficient physically unclonable function based on k-winners-take-all,” Electronics Letters, 2016.
  24. Mohammad Faisal Amir, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, “Exploration of Si/Ge Tunnel FET Bit Cells for Ultra-low Power Embedded Memory,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2016.
  25. Denny Lie, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, “Impact of Heterogeneous Technology Integration on the Power, Performance, and Quality of a 3D Image Sensor,” IEEE Transactions on Multi-Scale Computing Systems, 2016.
  26. Amit Ranjan Trivedi, Khondker Ahmed, and Saibal Mukhopadhyay, “Negative Gate Transconductance in Gate/Source Overlapped Heterojunction Tunnel FET and application to Single Transistor Phase Encoder,” IEEE Electron Device Letters, 2015.
  27. Amit Ranjan Trivedi, Suman Datta, and Saibal Mukhopadhyay, “Application of Silicon-Germanium Source Tunnel-FET to Enable Ultralow Power Cellular Neural Network-Based Associative Memory,” IEEE Transaction of Electron Devices, vol. 61, no. 11, Nov. 2014.
  28. Amit Ranjan Trivedi, Amith Singhee, Pranita Kerber, Takashi Ando, David Frank, and Saibal Mukhopadhyay, “A Simulation study of Oxygen vacancy induced variability in high-k/metal-gate SOI FinFET,” IEEE Transaction of Electron Devices, vol. 61, no. 5, May 2014.
  29. Amit Ranjan Trivedi and Saibal Mukhopadhyay, “Potential of SiGe Tunneling Nanowires for Ultra-low Power Image Processing,” IEEE Transaction of Nanotechnology, vol. 31, no. 4, July 2014.
  30. Amit Ranjan Trivedi and Saibal Mukhopadhyay, “In-situ Power Gating Efficiency Learner for Self Adaptive Power Gating,” IEEE Transaction of Circuits and Systems II, vol. 61, no. 5, May 2014.
  31. Wen Yueh, Subho Chatterjee, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, “Performance and Robustness of 3D integrated SRAM Considering Tier-to-tier Thermal and Supply Cross-talk,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 3, no. 6, June 2013.
  32. Tarun Kumar Agarwal, Amit Ranjan Trivedi, Vaidyanathan Subramanian, and M. Jagadesh Kumar, “Compact Modeling of Partially Depleted Silicon-on-Insulator Drain-Extended MOSFET (DEMOS) including High-voltage and Floating Body Effects,” IEEE Transaction of Electron Devices, vol. 58, no. 10, Oct 2011.
  33. Amit Ranjan Trivedi and Saibal Mukhopadhyay, “Through-Oxide-Via-Induced Back-Gate Effect in 3-D Integrated FDSOI Devices,” IEEE Electron Device Letters, vol. 32, no. 8, 2011.
  34. Amit Ranjan Trivedi and Supriyo Bandyopadhyay, “Single spin Toffoli-Fredkin logic gate,” Journals of Applied Physics, vol. 103, no. 10, May 2008.
  35. Amit Ranjan Trivedi, Supriyo Bandyopadhyay, and M. Cahay, “Switching Voltage, Dynamic power Dissipation and on-to-off conductance ratio of a spin field effect transistor” IET Circuits, Devices & Systems, vol. 1, no. 6, Dec. 2007.