Conferences

  1. Shamma Nasrin, Srikanth Ramakrishna, Theja Tulabandhula, and Amit Ranjan Trivedi. "Supported-BinaryNet: Bitcell Array-Based Weight Supports for Dynamic Accuracy-Energy Trade-Offs in SRAM-Based Binarized Neural Network." In IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
  2. Ahish Shylendra, Priyesh Shukla, Swarup Bhunia, and Amit Ranjan Trivedi. "Fault attack detection in AES by monitoring power side-channel statistics." In IEEE International Symposium on Quality Electronic Design (ISQED), 2020.
  3. Ahish Shylendra, Sina Haji Alizad, Priyesh Shukla, and Amit Ranjan Trivedi. "Non-parametric Statistical Density Function Synthesizer and Monte Carlo Sampler in CMOS." IEEE International Conference on VLSI Design (VLSID), 2020.
  4. Shamma Nasrin, Justine L. Drobitch, Supriyo Bandyopadhyay, and Amit Ranjan Trivedi. "Mixed-mode Magnetic Tunnel Junction-based Deep Belief Network." IEEE International Conference on Nanotechnology (IEEE-NANO), 2019.
  5. Alberto Gianelli, Nick Iliev, Shamma Nasrin, Mariagrazia Graziano, and Amit Ranjan Trivedi. "Low power speaker identification using look up-free Gaussian mixture model in CMOS." IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2019.
  6. Shih-Chang Hung, Nick Iliev, Balajee Vamanan and Amit Ranjan Trivedi, "Self-Organizing Maps-based Flexible and High-Speed Packet Classification in Software Defined Networking," IEEE International Conference on VLSI Design (VLSID), 2019.
  7. Dinesh Rajasekharan, Amit Ranjan Trivedi and Yogesh Chauhan, "Neuromorphic Circuits on FDSOI Technology for Computer Vision Applications," IEEE International Conference on VLSI Design (VLSID), 2019.
  8. Ahish Shylendra, Swarup Bhunia, and Amit Ranjan Trivedi "Intrinsic and Database-free Watermarking in ICs by Exploiting Process and Design Dependent Variability in Metal-Oxide-Metal Capacitances," IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2018.
  9. Amit Ranjan Trivedi and Ahish Shylendra, "Ultralow Power Acoustic Feature-scoring using Gaussian I-V Transistors," ACM Design Automation Conference (DAC), 2018.
  10. Dinesh Rajasekharan, Sarvesh S Chauhan, Amit Ranjan Trivedi, and Yogesh Singh Chauhan, "Energy and Area Efficient Tunnel FET-based Spiking Neural Networks," IEEE Electron Devices Technology and Manufacturing Conference (EDTM), 2018.
  11. Nick Iliev and Amit Trivedi, "Low Power Spatial Localization of Mobile Sensors with Recurrent Neural Network," IEEE Internation Conference on Computer Design (ICCD), 2017.
  12. Amit Ranjan Trivedi and Saibal Mukhopadhyay, "CMOS-based Stochastically Spiking Neural Network for Optimization under Uncertainties," GOMACTech Conference, 2017.
  13. Tonmoy Dhar, Swarup Bhunia, and Amit Ranjan Trivedi, "A Solitary Protection Measure Against Scan Chain, Fault Injection, and Power Analysis Attacks on AES," IEEE Mid-west Symposium of Circuits and Systems (MWSCAS), 2017.
  14. Dinesh Rajasekharan, Tapas Dutta, Amit Ranjan Trivedi, Yogesh Singh Chauhan, "Energy-efficient spiking neural networks based on Tunnel FET," IEEE International Conference on Emerging Electronics (ICEE), 2016.
  15. Amit Ranjan Trivedi and Susmita Dey Manasi, "A Comparative Study of Si/Ge and GaSb/InAs Tunnel FET-based Cellular Neural Network," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.
  16. Amit Ranjan Trivedi, Suman Datta, and Saibal Mukhopadhyay "Ultralow Power Neuromorphic Associative Processing with Si/Ge and InAs/GaSb Heterojunction TFET," GOMACTech conference, 2016.
  17. Susmita Dey Manasi and Amit Ranjan Trivedi, "Gate/Source-Overlapped Heterojunction Tunnel FET-based LAMSTAR Neural Network and its Application to EEG Signal Classification," IEEE Joint Conference on Neural Networks (IJCNN), 2016.
  18. Amit Ranjan Trivedi, Rahul Pandey, Huichu Liu, Suman Datta, and Saibal Mukhopadhyay. “Gate/Source overlapped heterojunction tunnel FET for non-Boolean associative processing with plasticity,” IEEE International Electron Devices Meeting (IEDM), 2015.
  19. Sravan Marella, Amit Ranjan Trivedi, Saibal Mukhopadhyay, and Sachin S. Sapatnekar. “Optimization of FinFET-based circuits using a dual gate pitch technique,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015.
  20. Mohammad Faisal Amir, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, “A Tunnel-FET SRAM Array for Energy-Efficient Embedded Memory Blocks in Reconfigurable Computing Platforms,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2014.
  21. Amit Ranjan Trivedi and Saibal Mukhopadhyay, “Si/Ge Tunneling Nanowires based Low Power Cellular Neural Network,” GOMACTech conference, 2014.
  22. Amit Ranjan Trivedi, Mohammad Faisal Amir, and Saibal Mukhopadhyay, “Ultralow Power Electronics with Si/Ge Tunnel FET,” IEEE Design Automation and Test in Europe, 2014.
  23. Krishnamurthy Yeleswarapu, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, “Simulation of the TSV-to-Device Coupling in 3D ICs for Short Channel Strained Silicon Transistors,” IEEE Electrical Performance of Electronic Packaging and Systems, 2013.
  24. Amit Ranjan Trivedi, Sergio Carlo, and Saibal Mukhopadhyay, “Exploring Tunnel-FET for ultra-low power analog applications: A case study for Operational Transconductance Amplifier,” ACM Design Automation Conference, 2013.
  25. Amit Ranjan Trivedi and Saibal Mukhopadhyay, “Self Adaptive Power-Gating Scheme by On-Line Characterization of Energy Inflection Activity,” SRC TECHCON, 2012.
  26. Amit Ranjan Trivedi and Saibal Mukhopadhyay, “Self-Adaptive Power Gating with Test Circuit for On-line Characterization of Energy Inflection Activity," IEEE VLSI Test Symposium, 2012.
  27. Wen Yueh, Subho Chatterjee, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, “On the Parameteric Failures of SRAM in a 3D-die Stack considering Tier-to-Tier Supply Cross-talk,” IEEE VLSI Test Symposium, 2012.
  28. S. Parthasarathy, Amit Ranjan Trivedi, S. Sirohi, R. Groves, M. Olsen, Y. S. Chauhan, M. Carroll, D. Kerr, A. Tombak, P. Mason, “RF SOI Switch FET Design and Modeling Trade-offs for GSM Applications,” IEEE International Conference on VLSI Design, 2010.