2017 J[16] Susmita Dey Manasi, Md Mamun Al-Rashid, Jayasimha Atulasimha, Supriyo Bandyopadhyay, and Amit Ranjan Trivedi, "Skewed Straintronic Magnetotunneling-Junction-Based Ternary Content-Addressable Memory-Part II," IEEE Transactions on Electron Devices , 2017.
J[15] Susmita Dey Manasi, Md Mamun Al-Rashid, Jayasimha Atulasimha, Supriyo Bandyopadhyay, and Amit Ranjan Trivedi, "Skewed Straintronic Magnetotunneling-Junction-Based Ternary Content-Addressable Memory-Part I," IEEE Transactions on Electron Devices , 2017. [read]
J[14] Tapas Dutta, Girish Pahwa, Amit Ranjan Trivedi, Saurabh Sinha, Amit Agarwal, and Yogesh Singh Chauhan, "Performance Evaluation of 7 nm Node Negative Capacitance FinFET based SRAM," IEEE Electron Device Letters , 2017. [read]
2016 J[13] Tonmoy Dhar and Amit Ranjan Trivedi, "Area and energy-efficient physically unclonable function based on k-winners-take-all," Electronics Letters , 2016. [read]
J[12] Mohammad Faisal Amir, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, "Exploration of Si/Ge Tunnel FET Bit Cells for Ultra-low Power Embedded Memory," IEEE Journal on Emerging and Selected Topics in Circuits and Systems , 2016. [read]
J[11] Denny Lie, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, “Impact of Heterogeneous Technology Integration on the Power, Performance, and Quality of a 3D Image Sensor,” IEEE Transactions on Multi-Scale Computing Systems , 2016. [read]
2015 J[10] Amit Ranjan Trivedi, Khondker Ahmed, and Saibal Mukhopadhyay, “Negative Gate Transconductance in Gate/Source Overlapped Heterojunction Tunnel FET and application to Single Transistor Phase Encoder,” IEEE Electron Device Letters , 2015. [read]
2014 J[9] Amit Ranjan Trivedi, Suman Datta, and Saibal Mukhopadhyay, “Application of Silicon-Germanium Source Tunnel-FET to Enable Ultralow Power Cellular Neural Network-Based Associative Memory,” IEEE Transaction of Electron Devices , vol. 61, no. 11, Nov. 2014. [read]
J[8] Amit Ranjan Trivedi, Amith Singhee, Pranita Kerber, Takashi Ando, David Frank, and Saibal Mukhopadhyay, “A Simulation study of Oxygen vacancy induced variability in high-k/metal-gate SOI FinFET,” IEEE Transaction of Electron Devices , vol. 61, no. 5, May 2014. [read]
J[7] Amit Ranjan Trivedi and Saibal Mukhopadhyay, “Potential of SiGe Tunneling Nanowires for Ultra-low Power Image Processing,” IEEE Transaction of Nanotechnology , vol. 31, no. 4, July 2014. [read]
J[6] Amit Ranjan Trivedi and Saibal Mukhopadhyay, “In-situ Power Gating Efficiency Learner for Self Adaptive Power Gating,” IEEE Transaction of Circuits and Systems II , vol. 61, no. 5, May 2014. [read]
2013 J[5] Wen Yueh, Subho Chatterjee, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, “Performance and Robustness of 3D integrated SRAM Considering Tier-to-tier Thermal and Supply Cross-talk,” IEEE Transactions on Components, Packaging and Manufacturing Technology , vol. 3, no. 6, June 2013. [read]
2011 J[4] Tarun Kumar Agarwal, Amit Ranjan Trivedi, Vaidyanathan Subramanian, and M. Jagadesh Kumar, “Compact Modeling of Partially Depleted Silicon-on-Insulator Drain-Extended MOSFET (DEMOS) including High-voltage and Floating Body Effects,” IEEE Transaction of Electron Devices , vol. 58, no. 10, Oct 2011. [read]
J[3] Amit Ranjan Trivedi and Saibal Mukhopadhyay, “Through-Oxide-Via-Induced Back-Gate Effect in 3-D Integrated FDSOI Devices,” IEEE Electron Device Letters , vol. 32, no. 8, 2011. [read]
2008 J[2] Amit Ranjan Trivedi and Supriyo Bandyopadhyay, “Single spin Toffoli-Fredkin logic gate,” Journals of Applied Physics , vol. 103, no. 10, May 2008. [read]
2007 J[1] Amit Ranjan Trivedi, Supriyo Bandyopadhyay, and M. Cahay, “Switching Voltage, Dynamic power Dissipation and on-to-off conductance ratio of a spin field effect transistor” IET Circuits, Devices & Systems , vol. 1, no. 6, Dec. 2007. [read]