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Negative gate transconductance in Heterojunction Tunnel FET: We showed that a gate/source overlapped heterojunction TFET exhibits negative gate transconductance (NGT) and a Gaussian-shaped IDS-VGS. At a higher VGS, depletion region in the gate-overlapped source reduces the electric field along channel resulting in reduced band-to-band-tunneling and NGT. [read more]
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Non-Boolean associative processing: We have demonstrated area/energy-efficient associative processing exploiting Gaussian IDS-VGS of SO-HTFET. Unique characteristics of SO-HTFET reduce associative processing distance-computing-cell to just one single transistor. [read more]
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Tunnel FET-based ultralow power cellular neural computing: We have demonstrated Si/Ge tunnel junction TFET-based ultralow power cellular neural network (CNN) for image processing and associative memory applications. [read more]
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In situ power-gating efficiency learner: We demonstrated a novel in situ power-gating efficiency learner circuit to characterize the tradeoff between leakage saving and transition energy overheads. A self-adaptive power-gating adaptively configures the system in power-gated/non-power-gated mode for a minimal wasted power. [read more]
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Oxygen vacancy-induced variability in nanoscaled high-κ/metal gate transistors: We demonstrated the implications of high-κ/metal gate dielectric defect, oxygen vacancy (OV), in inducing transistor threshold voltage variability. As count and spatial allocation of positively charged OVs varies from the device-to-device, it induces significant local variability in the gate workfunction. [read more]